The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2022

Filed:

Jan. 13, 2021
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Juergen Hoegerl, Regensburg, DE;

Ordwin Haase, Taufkirchen, DE;

Tobias Kist, Effeltrich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/492 (2006.01); H01L 23/373 (2006.01); H01L 23/495 (2006.01); H01L 25/16 (2006.01); H01L 23/31 (2006.01); H01L 29/16 (2006.01); H01L 21/56 (2006.01); H01L 21/52 (2006.01); H01L 23/433 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 21/52 (2013.01); H01L 21/56 (2013.01); H01L 23/3121 (2013.01); H01L 23/3735 (2013.01); H01L 23/433 (2013.01); H01L 23/492 (2013.01); H01L 23/49524 (2013.01); H01L 25/16 (2013.01); H01L 29/1608 (2013.01);
Abstract

A semiconductor package includes an encapsulant body; an upper electrically conductive element having an outwardly exposed metal surface; a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer; a first electrically conductive spacer between the upper electrically conductive element and the upper electrically conductive layer; a power semiconductor chip between the upper electrically conductive element and the upper electrically conductive layer; and a second electrically conductive spacer between the upper electrically conductive element and the power semiconductor chip, a first carrier region of the upper electrically conductive layer is connected to a first power terminal, a second carrier region of the upper electrically conductive layer is alongside the first carrier region and is connected to a phase terminal, a first region of the upper electrically conductive element is connected to a second power terminal.


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