The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2022

Filed:

Jun. 30, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yunbiao Lin, Shanghai, CN;

Changliang Wang, Bellevue, WA (US);

Satyanantha Ramagopal Musunuri, Bangalore, IN;

David Puffer, Tempe, AZ (US);

David J. Cowperthwaite, Portland, OR (US);

Bryan R. White, Chandler, AZ (US);

Balaji Vembu, Folsom, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06F 3/14 (2006.01); G06F 9/451 (2018.01); G09G 5/00 (2006.01); G09G 5/36 (2006.01); G06F 12/10 (2016.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06F 3/14 (2013.01); G06F 9/452 (2018.02); G06F 12/10 (2013.01); G06F 12/1009 (2013.01); G06T 1/60 (2013.01); G09G 5/00 (2013.01); G09G 5/363 (2013.01); G09G 2360/06 (2013.01); G09G 2370/022 (2013.01); G09G 2370/042 (2013.01); G09G 2370/047 (2013.01);
Abstract

An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.


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