The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

Sep. 24, 2020
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Hyangkeun Yoo, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 31/0312 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78391 (2014.09); H01L 29/161 (2013.01); H01L 29/1608 (2013.01); H01L 29/513 (2013.01); H01L 29/516 (2013.01); H01L 29/785 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01);
Abstract

A ferroelectric memory device according to one embodiment includes a semiconductor substrate, a fin structure disposed on the semiconductor substrate and having a trench, the trench having a bottom surface and a sidewall surface; a ferroelectric layer disposed on the bottom surface and the sidewall surface of the trench; a plurality of resistor layers stacked vertically in the trench, each resistor layer of the plurality of resistor layers having a different electrical resistance; and a gate electrode layer electrically connected to the each resistor layer in the plurality of resistor layers. The plurality of resistor layers are disposed between the gate electrode layer and the ferroelectric layer.


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