The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Jul. 20, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chung-Ting Ko, Kaohsiung, TW;

Han-Chi Lin, Kaohsiung, TW;

Chunyao Wang, Zhubei, TW;

Ching Yu Huang, Baoshan Township, TW;

Tze-Liang Lee, Hsinchu, TW;

Yung-Chih Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/762 (2006.01); H01L 21/3213 (2006.01); H01L 21/02 (2006.01); H01L 21/3115 (2006.01); H01L 29/66 (2006.01); H01L 21/3065 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7843 (2013.01); H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H01L 21/0234 (2013.01); H01L 21/02208 (2013.01); H01L 21/3065 (2013.01); H01L 21/31155 (2013.01); H01L 21/32133 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01);
Abstract

A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.


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