The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2022
Filed:
Jan. 26, 2021
Applicant:
Sandisk Technologies Llc, Addison, TX (US);
Inventors:
Shinsuke Yada, Yokkaichi, JP;
Hiroyuki Ogawa, Yokkaichi, JP;
Assignee:
SANDISK TECHNOLOGIES LLC, Addison, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/00 (2006.01); G11C 16/16 (2006.01); G11C 16/30 (2006.01); G11C 16/24 (2006.01); G11C 16/08 (2006.01); H01L 27/11524 (2017.01); H01L 27/11582 (2017.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract
A method of erasing vertical NAND strings from a source side of the vertical NAND strings includes applying a relatively high erase voltage to a source line, applying a relatively low voltage or 0 V to bit lines, applying a first drain-select-level voltage that is less than the erase voltage to one of the first drain-select-level electrically conductive layers, and applying a second drain-select-level voltage that is greater than the first drain-select-level voltage and not greater than the erase voltage to one of the second drain-select-level electrically conductive layers.