The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2022
Filed:
Sep. 28, 2018
Cadence Design Systems, Inc., San Jose, CA (US);
Feng Miao, Shanghai, CN;
Jing Wang, Shanghai, CN;
Zhen Mu, North Chelmsford, MA (US);
Xuegang Zeng, Westborough, MA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include performing, using a processor, a simulation of a multi-layered electronic structure and extracting a circuit model of the multi-layered electronic structure, wherein the circuit model includes at least two plates. Embodiments may also include extracting one or more parasitic parameters of at least one via associated with the circuit model and calculating a coupling coefficient associated with a controlled source of the circuit model. Embodiments may further include extracting a transmission line mode from the circuit model and linking the circuit model, at least one via, and the transmission line mode to an external circuit to generate a modeled system. Embodiments may also include solving the modeled system using a modified nodal analysis.