The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Jun. 26, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert L. Pelt, Austin, TX (US);

Hong Wang, Santa Clara, CA (US);

Arifur Rahman, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 8/41 (2018.01); G06F 12/126 (2016.01); G06F 9/52 (2006.01); G06F 12/0862 (2016.01); G06F 12/0871 (2016.01); G06F 9/445 (2018.01); G06F 12/0811 (2016.01); G06F 12/0888 (2016.01); G06F 9/50 (2006.01); G06F 30/30 (2020.01); G06F 30/34 (2020.01); G06F 30/327 (2020.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 8/445 (2013.01); G06F 8/4442 (2013.01); G06F 9/44505 (2013.01); G06F 9/5016 (2013.01); G06F 9/52 (2013.01); G06F 12/0811 (2013.01); G06F 12/0862 (2013.01); G06F 12/0871 (2013.01); G06F 12/0888 (2013.01); G06F 12/126 (2013.01); G06F 30/30 (2020.01); G06F 30/327 (2020.01); G06F 30/34 (2020.01); G06F 2212/1016 (2013.01); G06F 2212/601 (2013.01);
Abstract

A system for running one or more applications is provided. Each application may require memory services that can be accelerated using configurable memory assistance circuits associated with different levels of a memory hierarchy. Integrated circuit design tools may be used to generate configuration data for programming the configurable memory assistance circuits. During compile time, the design tools may identify memory service patterns in a source code, match the identified memory service patterns to corresponding templates, parameterize the matching templates, and then synthesize the parameterized templates to produce the configuration data. During run time, a memory assistance scheduler may map the memory services required by each application to available memory assistance circuits in the system. The mapped memory assistance circuits are programmed by the configuration data to provide the desired memory service capability.


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