The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

May. 08, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Leo Aqrabawi, Portland, OR (US);

Chia-hung S. Kuo, Folsom, CA (US);

James G. Hermerding, II, Vancouver, WA (US);

Premanand Sakarda, Acton, MA (US);

Bijan Arbab, San Diego, CA (US);

Kelan Silvester, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/3234 (2019.01); G06F 12/0815 (2016.01); G06N 5/04 (2006.01); G06N 20/00 (2019.01); G06F 1/3203 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3234 (2013.01); G06F 12/0815 (2013.01); G06N 5/04 (2013.01); G06N 20/00 (2019.01); G06F 1/3203 (2013.01); G06F 2212/1032 (2013.01);
Abstract

A machine-learning (ML) scheme running a software driver stack to learn user habits of entry into low power states, such as Modern Connect Standby (ModCS), and duration depending on time of day, and/or system telemetry. The ML creates a High Water Mark (HWM) number of dirty cache lines (DL) as a hint to a power agent. A power agent algorithm uses these hints and actual system's number of DL to inform the low power state entry decision (such as S0i4 vs. S0i3 entry decision) for a computing system.


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