The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2022

Filed:

Oct. 31, 2019
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Zhongze Wang, San Diego, CA (US);

Xia Li, San Diego, CA (US);

Xiaochun Zhu, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/08 (2006.01); G06N 3/063 (2006.01); G11C 11/419 (2006.01); G11C 11/412 (2006.01); G11C 11/21 (2006.01);
U.S. Cl.
CPC ...
G06N 3/0635 (2013.01); G06N 3/063 (2013.01); G11C 11/21 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01);
Abstract

Certain aspects provide a circuit for in-memory computation. The circuit generally includes a first memory cell, and a first computation circuit. The first computation circuit may include a first switch having a control input coupled to an output of the first memory cell, a second switch coupled between a node of the first computation circuit and the first switch, a control input of the second switch being coupled to a discharge word-line (DCWL), a capacitive element coupled between the node and a reference potential node, a third switch coupled between the node and a read bit-line (RBL), and a fourth switch coupled between the node and an activation (ACT) line.


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