The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2022

Filed:

Mar. 26, 2021
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Sourav Kumar Sircar, Noida, IN;

Alwin Gupta, Noida, IN;

Marc Heyberger, Mandelieu, FR;

Manish Bhatia, Ghaziabad, IN;

Manish Garg, Gautam Budh Nagar, IN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/3312 (2020.01); G06F 30/398 (2020.01); G06F 30/3315 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/3312 (2020.01); G06F 30/3315 (2020.01); G06F 30/398 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01);
Abstract

Disclosed are methods, systems, and articles of manufacture for implementing electronic design closure with reduction techniques. A timing graph and compact timing data for an analysis view of a set of analysis views may be determined for an electronic design. A reduced set of dominant analysis views may be determined based at least in part upon a result of a timing dominance analysis. Timing data may be loaded for at least the reduced set of dominant analysis views; and a design closure task may be performed on the electronic design using at least the timing data and the reduced set of dominance analysis views.


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