The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2022

Filed:

Sep. 27, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ranganath Sunku, Hillsboro, OR (US);

Dinesh Kumar, Portland, OR (US);

Irene Liew, Gilbert, AZ (US);

Kavindya Deegala, Portland, OR (US);

Sravanthi Tangeda, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 9/50 (2006.01); H04L 12/931 (2013.01); G06F 15/16 (2006.01); H04L 15/16 (2006.01); H04L 49/00 (2022.01); H04L 41/0823 (2022.01); H04L 12/70 (2013.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 9/5027 (2013.01); G06F 9/5077 (2013.01); H04L 41/0823 (2013.01); H04L 49/70 (2013.01); G06F 2009/4557 (2013.01); G06F 2009/45595 (2013.01); H04L 2012/5631 (2013.01);
Abstract

Technologies for adaptive platform resource management include a compute node to manage a processor core mapping scheme between virtual machines (VMs) and a virtual switch of the compute node via a set of virtual ports. The virtual switch is also coupled to a network interface controller (NIC) of the compute node via another set of virtual ports. Each of the VMs is configured to either provide ingress or egress to the NIC or provide ingress/egress across the VMs, via the virtual ports. The virtual ports for providing ingress or egress to the NIC are pinned to a same processor core of a processor of the compute node, and each of the virtual ports for providing ingress and/or egress across the VMs are pinned to a respective processor core of the processor such that data is transferred across VMs by coupled virtual ports that are pinned to the same processor core.


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