The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2022
Filed:
Apr. 26, 2021
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Alexander John Wakefield, Fort Lauderdale, FL (US);
Khader Abdel-Hafez, Sunnyvale, CA (US);
Assignee:
Synopsys, Inc., Mountain View, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 11/34 (2006.01); G06F 11/30 (2006.01); G06F 11/27 (2006.01); G06F 11/263 (2006.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 11/263 (2013.01); G06F 11/27 (2013.01); G06F 11/3058 (2013.01); G06F 11/3409 (2013.01); G06F 11/3447 (2013.01);
Abstract
A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.