The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2022

Filed:

Oct. 20, 2020
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Jae Gil Lee, Seoul, KR;

Kun Young Lee, Seoul, KR;

Hyangkeun Yoo, Seongnam-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11597 (2017.01); H01L 27/1159 (2017.01); H01L 27/11551 (2017.01); H01L 27/11556 (2017.01); H01L 27/11585 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11597 (2013.01); H01L 27/1159 (2013.01); H01L 27/11551 (2013.01); H01L 27/11556 (2013.01); H01L 27/11585 (2013.01);
Abstract

A semiconductor device according to an embodiment includes a substrate, and a gate structure disposed over the substrate. The gate structure includes a hole pattern including a central axis extending in a direction perpendicular to a surface of the substrate. The gate structure includes a gate electrode layer and an interlayer insulation layer, which are alternately stacked along the central axis. The semiconductor device includes a ferroelectric layer disposed adjacent to a sidewall surface of the gate electrode layer inside the hole pattern, and a channel layer disposed adjacent to the ferroelectric layer inside the hole pattern. In this case, one of the gate electrode layer and the interlayer insulation layer protrudes toward the central axis of the hole pattern relative to the other one of the gate electrode layer and the interlayer insulation layer.


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