The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2022
Filed:
Jan. 11, 2021
Nanya Technology Corporation, New Taipei, TW;
Yi-Jen Lo, New Taipei, TW;
NANYA TECHNOLOGY CORPORATION, New Taipei, TW;
Abstract
A method of manufacturing a wafer-to-wafer interconnection structure includes forming a first etching stop layer with at least two portions on a first surface of a first substrate, and forming a void in one portion of the first etching stop layer. A second etching stop layer is formed on a first surface of a second substrate, and then the first surfaces of the first substrate and the second substrate are bonded, wherein the second etching stop layer is aligned to the void. By using the first and the second etching stop layers as etching stop layers, a first opening is formed from a second surface of the first substrate into the first substrate, and a second opening is formed through the void to the second substrate. A first TSV (through silicon via) is formed in the first opening, and a second TSV is formed in the second opening.