The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2022
Filed:
Jan. 16, 2019
Intel Corporation, Santa Clara, CA (US);
Jonathan W. Thibado, Beaverton, OR (US);
Jeffory L. Smalley, East Olympia, WA (US);
John C. Gulick, Portland, OR (US);
Phi Thanh, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a plurality of heater traces in a substrate. The RGA interposer also includes a plurality of vias in the substrate. The vias extend vertically from the bottom surface to the top surface of the substrate. The RGA interposer may have one of the vias between two of the heater traces, wherein the vias have a z-height that is greater than a z-height of the heater traces. The heater traces may be embedded in a layer of the substrate, where the layer of the substrate is between top ends and bottom ends of the vias. Each of the plurality of heater traces may include a via filament interconnect coupled to a power source and a ground source. The heater traces may be resistive heaters.