The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2022

Filed:

Feb. 08, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Paolo Amato, Treviglio, IT;

Marco Dallabora, Melegnano, IT;

Daniele Balluchi, Cernusco Sul Naviglio, IT;

Danilo Caraccio, Milan, IT;

Emanuele Confalonieri, Lesmo, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 13/00 (2006.01); G11C 7/22 (2006.01); G06F 11/10 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G06F 11/1068 (2013.01); G11C 7/222 (2013.01); G11C 13/0023 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); G11C 29/44 (2013.01); G11C 2029/0411 (2013.01);
Abstract

An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.


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