The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2022
Filed:
Jun. 15, 2022
Monolithic 3d Inc., Klamath Falls, OR (US);
Zvi Or-Bach, Haifa, IL;
Zeev Wurman, Palo Alto, CA (US);
MONOLITHIC 3D INC., Klamath Falls, OR (US);
Abstract
A method of designing 3D Integrated Circuits including: partitioning at least one design into at least two levels, a first and second level, where the first level includes logic, the second level includes memory; and then receiving a first placement of at least portion of the second level, where the first placement includes a placement of a first memory array, where the Circuit includes a plurality of connections between the first level and second level; performing a second placement of the first level based on the first placement, the performing a second placement includes using a placer computer executed, where the placer is a part of a Computer Aided Design tool, where the logic includes a first logic circuit configured to write data to the first memory array, and where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array.