The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2022

Filed:

Feb. 12, 2021
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Grishma Shah, San Jose, CA (US);

Daniel Tuers, Kapaa, HI (US);

Sahil Sharma, San Jose, CA (US);

Hua-Ling Cynthia Hsu, Fremont, CA (US);

Yenlung Li, San Jose, CA (US);

Min Peng, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0882 (2016.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0629 (2013.01); G06F 3/0614 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0207 (2013.01); G06F 12/0882 (2013.01);
Abstract

A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.


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