The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2022

Filed:

Feb. 19, 2021
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Asli Sahin, Danbury, CT (US);

Karen A. Nummy, Newburgh, NY (US);

Thomas Houghton, Marlboro, NY (US);

Kevin K. Dezfulian, Arlington, VA (US);

Kenneth J. Giewont, Hopewell Junction, NY (US);

Yusheng Bian, Ballston Lake, NY (US);

Assignee:

GLOBALFOUNDRIES U.S. INC., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/122 (2006.01); G02B 6/13 (2006.01);
U.S. Cl.
CPC ...
G02B 6/122 (2013.01); G02B 6/13 (2013.01);
Abstract

A photonics integrated circuit includes a semiconductor substrate; a buried insulator layer positioned over the semiconductor substrate; and a back-end-of-line (BEOL) insulator stack over a first portion of the buried insulator layer. In addition, the PIC includes a silicon nitride (SiN) waveguide edge coupler positioned in a first region over the buried insulator layer and at least partially under the BEOL insulator stack. An oxide layer extends over a side of the BEOL insulator stack. The SiN waveguide edge coupler provides better power handling and fabrication tolerance than silicon waveguide edge couplers, despite the location under various BEOL layers. The PIC can also include silicon waveguide edger coupler(s).


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