The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2022

Filed:

Dec. 31, 2020
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Neha Srivastava, New Delhi, IN;

Ateet Mishra, Noida, IN;

Ankur Behl, New Delhi, IN;

Nancy Mishra, Noida, IN;

Kriti Garg, Kurukshetra, IN;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/135 (2006.01); G06F 30/3308 (2020.01); G06F 111/04 (2020.01); G06F 115/02 (2020.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/135 (2013.01); G06F 30/3308 (2020.01); G06F 2111/04 (2020.01); G06F 2115/02 (2020.01); H03K 2005/00019 (2013.01);
Abstract

A clock sweeping system includes multiple delay elements and a selection circuit. The delay elements are configured to generate multiple delayed clock signals. Each delay element is configured to receive an input signal and delay the input signal to generate a corresponding first delayed clock signal. The input signal is one of a first clock signal, a second clock signal, and a corresponding output signal generated by a previous delay element. The selection circuit is configured to select and output, based on a first select signal for a plurality of times, a corresponding second delayed clock signal as a first output clock signal. The selection circuit is further configured to select and output, based on a second select signal, one of the first and second clock signals as a second output clock signal. The first output clock signal is asynchronous with respect to the second output clock signal.


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