The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2022

Filed:

Jun. 10, 2021
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Li-Han Lu, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/76283 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01);
Abstract

The present disclosure provides a method for manufacturing a semiconductor structure having different filling layers. The method includes forming a multi-layer stack in a semiconductor substrate, wherein the multi-layer stack has a first filling layer and a second layer, the semiconductor substrate has two through vias, and two top portions of the multi-layer stack are respectively exposed through the two through vias. The method further includes recessing the multi-layer stack from the two through vias to respectively form two blind holes in the first filling layer and the second filling layer; selectively etching the second filling layer to form a global cavity between the two blind holes; filling the global cavity and the two blind holes with dielectric filling material to form an air void in the multi-layer stack; and forming a switch device over the semiconductor substrate, wherein the air void is formed under the switch device.


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