The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2022

Filed:

Jul. 23, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sung-woo Kim, Hwaseong-si, KR;

Jae-Kyu Lee, Seoul, KR;

Ki-seok Suh, Hwaseong-si, KR;

Hyeong-sun Hong, Seongnam-si, KR;

Yoo-sang Hwang, Suwon-si, KR;

Gwan-hyeob Koh, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 43/12 (2006.01); G11C 14/00 (2006.01); H01L 45/00 (2006.01); H01L 29/08 (2006.01); H01L 27/108 (2006.01); H01L 29/423 (2006.01); H01L 43/08 (2006.01); H01L 43/02 (2006.01); H01L 27/24 (2006.01); H01L 27/22 (2006.01); H01L 27/105 (2006.01); H01L 27/02 (2006.01); G11C 7/10 (2006.01); G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0036 (2013.01); G11C 7/10 (2013.01); G11C 11/005 (2013.01); G11C 14/009 (2013.01); G11C 14/0045 (2013.01); G11C 14/0081 (2013.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/1052 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10829 (2013.01); H01L 27/10852 (2013.01); H01L 27/10876 (2013.01); H01L 27/10885 (2013.01); H01L 27/10891 (2013.01); H01L 27/222 (2013.01); H01L 27/228 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 29/0847 (2013.01); H01L 29/4236 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 43/12 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/1608 (2013.01);
Abstract

An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.


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