The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2022
Filed:
Mar. 26, 2021
Applicant:
Altera Corporation, San Jose, CA (US);
Inventor:
Mark Bourgeault, Mississauga, CA;
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); H03K 19/173 (2006.01); G06F 30/39 (2020.01); G06F 30/331 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/3312 (2020.01); G06F 1/06 (2006.01); H03L 7/07 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G06F 1/06 (2013.01); G06F 30/331 (2020.01); G06F 30/3312 (2020.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H03K 19/1733 (2013.01); H03L 7/07 (2013.01); H03K 3/0375 (2013.01);
Abstract
An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.