The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Sep. 15, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Yao-Wen Chang, Taipei, TW;

Gung-Pei Chang, Taipei, TW;

Ching-Sheng Chu, Hsinchu County, TW;

Chern-Yow Hsu, Hsin-Chu County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/26 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/26 (2013.01); H01L 21/0228 (2013.01); H01L 21/02172 (2013.01); H01L 21/02304 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 21/76871 (2013.01); H01L 21/76889 (2013.01);
Abstract

The present disclosure provides a method for forming a semiconductor structure. The method includes the following operations. A metal layer is formed. An adhesion-enhancing layer is formed over the metal layer by a silicide operation. A dielectric stack is formed over the adhesion-enhancing layer. A trench is formed in the dielectric stack by removing a portion of dielectric stack aligning with the metal layer. A barrier layer is formed conforming to the sidewall of the trench. A high-k dielectric layer is formed conforming to the barrier layer. A contact is formed in the trench and be connected to the metal layer.


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