The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Dec. 04, 2020
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Desmond Jia Jun Loy, Singapore, SG;

Eng Huat Toh, Singapore, SG;

Shyue Seng Tan, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2436 (2013.01); H01L 45/1675 (2013.01);
Abstract

Structures including non-volatile memory elements and methods of fabricating a structure including non-volatile memory elements. First, second, and third non-volatile memory elements each include a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is coupled to the first electrode of the third non-volatile memory element.


Find Patent Forward Citations

Loy, Desmond Jia Jun. (2022). Multi-level cell configurations for non-volatile memory elements in a bitcell (U.S. Patent No. 11476303). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11476303

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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