The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2022
Filed:
Apr. 14, 2021
Kamal M. Karda, Boise, ID (US);
Ramanathan Gandhi, Singapore, SG;
Hong LI, Albuquerque, NM (US);
Haitao Liu, Boise, ID (US);
Durai Vishak Nirmal Ramaswamy, Boise, ID (US);
Sanh D. Tang, Meridian, ID (US);
Scott E. Sills, Boise, ID (US);
Kamal M. Karda, Boise, ID (US);
Ramanathan Gandhi, Singapore, SG;
Hong Li, Albuquerque, NM (US);
Haitao Liu, Boise, ID (US);
Durai Vishak Nirmal Ramaswamy, Boise, ID (US);
Sanh D. Tang, Meridian, ID (US);
Scott E. Sills, Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
A device comprises a vertical transistor. The vertical transistor comprises a semiconductive pillar, at least one gate electrode, a gate dielectric material, and void spaces. The semiconductive pillar comprises a source region, a drain region, and a channel region extending vertically between the source region and the drain region, the channel region comprising a semiconductive material having a band gap greater than 1.65 electronvolts. The at least one gate electrode laterally neighbors the semiconductive pillar. The gate dielectric material is laterally between the semiconductive pillar and the at least one gate electrode. The void spaces are vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related electronic systems and methods are also disclosed.