The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Aug. 06, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Scott E. Sills, Boise, ID (US);

John A. Smythe, III, Boise, ID (US);

Si-Woo Lee, Boise, ID (US);

Gurtej S. Sandhu, Boise, ID (US);

Armin Saeedi Vahdat, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/786 (2006.01); H01L 29/78 (2006.01); H01L 27/11578 (2017.01); H01L 27/11597 (2017.01);
U.S. Cl.
CPC ...
H01L 27/10802 (2013.01); H01L 27/10805 (2013.01); H01L 27/11578 (2013.01); H01L 27/11597 (2013.01); H01L 29/7841 (2013.01); H01L 29/7855 (2013.01); H01L 29/7869 (2013.01);
Abstract

Systems, methods and apparatus are provided for a three-node access device in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. An etchant process is used to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent a first region. The first region is selectively etched to form a first horizontal opening removing the sacrificial material a first horizontal distance back from the first vertical opening. A first source/drain material, a replacement channel material having backchannel passivation, and a second source/drain material are deposited in the first horizontal opening to form the three-node access device for a memory cell among the arrays of vertically stacked memory cells.


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