The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Dec. 21, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rajkishore Barik, Santa Clara, CA (US);

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Xiaoming Chen, Shanghai, CN;

Dhawal Srivastava, Phoenix, AZ (US);

Anbang Yao, Beijing, CN;

Kevin Nealis, San Jose, CA (US);

Eriko Nurvitadhi, Portland, OR (US);

Sara S. Baghsorkhi, San Jose, CA (US);

Balaji Vembu, Folsom, CA (US);

Tatiana Shpeisman, Menlo Park, CA (US);

Ping T. Tang, Edison, NJ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/06 (2006.01); G06N 3/063 (2006.01); G06N 3/04 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06T 1/20 (2006.01); G06N 3/08 (2006.01); G06F 16/17 (2019.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 9/3001 (2013.01); G06F 9/3017 (2013.01); G06F 9/3851 (2013.01); G06F 9/3887 (2013.01); G06F 9/3895 (2013.01); G06F 16/17 (2019.01); G06N 3/0445 (2013.01); G06N 3/0454 (2013.01); G06N 3/084 (2013.01); G06T 1/20 (2013.01);
Abstract

One embodiment provides an apparatus comprising an instruction cache to store a plurality of instructions, a scheduler unit coupled to the instruction cache, the scheduler unit to schedule the plurality of instructions for execution, an instruction fetch and decode unit to decode the plurality of instructions to determine a set of operations to perform in response, one or more compute blocks to perform parallel multiply-accumulate operations based on the instruction fetch and decode unit decoding a first instruction of the plurality of instructions, and matrix multiplication logic to perform matrix multiplication operations based on the instruction fetch and decode unit decoding a second instruction of the plurality of instructions.


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