The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Mar. 27, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Zoran Zivkovic, Hertogenbosch, NL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/544 (2006.01); G06F 9/38 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3893 (2013.01); G06F 7/5443 (2013.01); G06F 9/3887 (2013.01); G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 9/30189 (2013.01);
Abstract

An apparatus and method for performing multiply-accumulate (MAC) operations on complex numbers to generate real results. For example, one embodiment of a processor comprises: a decoder to decode instructions including multiply-accumulate instructions; first and second source registers to store a first plurality of complex values and a second plurality of complex values, respectively, each complex value comprising a real value and an imaginary value; multiply-accumulate (MAC) execution circuitry coupled to the first and second source registers comprising multiplier circuitry, adder circuitry, and accumulator circuitry; mode selection circuitry to select between at least two execution modes for the MAC execution circuitry including a first mode in which the MAC execution circuitry is to perform complex multiply-accumulate operations using real and imaginary values from the first plurality of complex values and the second plurality of complex values and a second mode in which the MAC execution circuitry is to replace one or more of the real or imaginary values from the first and second plurality of complex values with one or more real or imaginary values specified in a set of scalar complex numbers or with zeroes.


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