The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2022
Filed:
Feb. 27, 2020
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Ze-Sian Lu, Hsinchu, TW;
Ting-Wei Chiang, New Taipei, TW;
Pin-Dai Sue, Tainan, TW;
Jung-Hsuan Chen, Hsinchu, TW;
Hui-Wen Li, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7831 (2013.01); H01L 27/0688 (2013.01); H01L 27/0922 (2013.01); H01L 29/42392 (2013.01); H01L 29/66484 (2013.01); H01L 29/7855 (2013.01); H01L 27/0924 (2013.01); H01L 27/2481 (2013.01);
Abstract
A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.