The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Jun. 11, 2020
Applicant:

Atomera Incorporated, Los Gatos, CA (US);

Inventors:

Hideki Takeuchi, San Jose, CA (US);

Yung-Hsuan Yang, San Jose, CA (US);

Assignee:

ATOMERA INCORPORATED, Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/267 (2006.01);
U.S. Cl.
CPC ...
H01L 29/152 (2013.01); H01L 29/1054 (2013.01); H01L 29/267 (2013.01); H01L 29/42368 (2013.01);
Abstract

A semiconductor device may include a semiconductor substrate, and shallow trench isolation (STI) regions in the semiconductor substrate defining an active region therebetween in the semiconductor substrate, with the active region having rounded shoulders adjacent the STI regions with an interior angle of at least 125°. The semiconductor device may further include a superlattice on the active region including stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may also include a semiconductor circuit on the substrate including the superlattice.


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