The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Jul. 29, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seok Han Park, Seongnam-si, KR;

Yong Seok Kim, Suwon-si, KR;

Hui-Jung Kim, Seongnam-si, KR;

Satoru Yamada, Yongin-si, KR;

Kyung Hwan Lee, Seoul, KR;

Jae Ho Hong, Hwaseong-si, KR;

Yoo Sang Hwang, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11597 (2017.01); H01L 27/1159 (2017.01); H01L 29/06 (2006.01); H01L 29/45 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11597 (2013.01); H01L 27/1159 (2013.01); H01L 28/40 (2013.01); H01L 29/0673 (2013.01); H01L 29/45 (2013.01); H01L 29/78391 (2014.09); H01L 29/78696 (2013.01);
Abstract

A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.


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