The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Jan. 16, 2020
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Robert Fehler, Regensburg, DE;

Eung San Cho, Torrance, CA (US);

Danny Clavette, Greene, RI (US);

Petteri Palm, Regensburg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/12 (2006.01); H01L 23/34 (2006.01); H01L 21/00 (2006.01); H05K 7/00 (2006.01); H05K 1/18 (2006.01); H05K 7/10 (2006.01); H05K 7/18 (2006.01); H01L 23/495 (2006.01); H01L 25/07 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 23/49513 (2013.01); H01L 23/49537 (2013.01); H01L 23/49562 (2013.01); H01L 24/06 (2013.01); H01L 24/37 (2013.01); H01L 24/40 (2013.01); H01L 24/84 (2013.01); H01L 25/072 (2013.01); H01L 2224/0603 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.


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