The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Dec. 18, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chai-Wei Chang, New Taipei, TW;

Po-Chi Wu, Zhubei, TW;

Wen-Han Fang, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823437 (2013.01); H01L 21/28123 (2013.01); H01L 21/823431 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 21/28088 (2013.01); H01L 21/31058 (2013.01); H01L 21/31144 (2013.01); H01L 29/517 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The method includes forming a gate material layer in the trench. The method includes forming a planarization layer over the gate material layer. The planarization layer includes a first material that is different from a second material of the gate material layer and a third material of the dielectric layer. The method includes performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench.


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