Array of integrated pixel and memory cells for deep in-sensor, in-memory computing

Abstract

Disclosed are embodiments of an integrated circuit structure (e.g., a processing chip), which includes an array of integrated pixel and memory cells configured for deep in-sensor, in-memory computing (e.g., of neural networks). Each cell incorporates a memory structure (e.g., DRAM structure or a ROM structure) with a storage node, which stores a first data value (e.g., a binary weight value), and a sensor connected to a sense node, which outputs a second data value (e.g., an analog input value). Each cell is selectively operable in a functional computing mode during which the voltage level on a bit line is adjusted as a function of both the first data value and the second data value. Each cell is further selectively operable in a storage node read mode. Furthermore, depending upon the type of memory structure (e.g., a DRAM structure), each cell is selectively operable in a storage node write mode.