The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2022

Filed:

Dec. 30, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ronen Hyatt, Haifa, IL;

Mark Debbage, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); H04L 41/5025 (2022.01); G06F 11/34 (2006.01); B25J 15/00 (2006.01); G06F 1/18 (2006.01); G06F 1/20 (2006.01); G06F 15/78 (2006.01); H05K 7/14 (2006.01); H05K 7/18 (2006.01); H05K 7/20 (2006.01); H04L 67/1008 (2022.01); H04L 41/0896 (2022.01); G06N 3/063 (2006.01); H04L 41/5019 (2022.01); H04L 41/14 (2022.01); G06F 21/10 (2013.01); G06Q 30/02 (2012.01); G06F 9/44 (2018.01); G06F 13/40 (2006.01); G06Q 10/06 (2012.01); H04L 49/40 (2022.01); G06F 9/48 (2006.01); H04L 9/40 (2022.01);
U.S. Cl.
CPC ...
G06F 9/5088 (2013.01); B25J 15/0014 (2013.01); G06F 1/183 (2013.01); G06F 1/20 (2013.01); G06F 9/505 (2013.01); G06F 11/3442 (2013.01); G06F 15/7807 (2013.01); G06F 15/7867 (2013.01); H04L 41/5025 (2013.01); H04L 67/1008 (2013.01); H05K 7/1489 (2013.01); H05K 7/18 (2013.01); H05K 7/20209 (2013.01); H05K 7/20736 (2013.01); G06F 9/44 (2013.01); G06F 9/4856 (2013.01); G06F 9/5061 (2013.01); G06F 13/4022 (2013.01); G06F 21/105 (2013.01); G06F 2200/201 (2013.01); G06N 3/063 (2013.01); G06Q 10/0631 (2013.01); G06Q 30/0283 (2013.01); H04L 41/0896 (2013.01); H04L 41/14 (2013.01); H04L 41/5019 (2013.01); H04L 49/40 (2013.01); H04L 63/0428 (2013.01); H05K 7/1498 (2013.01);
Abstract

Technologies for processing network packets a compute device with a network interface controller (NIC) that includes a host interface, a packet processor, and a network interface. The host interface is configured to receive a transaction from the compute engine, wherein the transaction includes latency-sensitive data, determine a context of the latency-sensitive data, and verify the latency-sensitive data against one or more server policies as a function of the determined context. The packet processor is configured to identify a trust associated with the latency-sensitive data, determine whether to verify the latency-sensitive data against one or more network policies as a function of the identified trust, apply the one or more network policies, and encapsulate the latency-sensitive data into a network packet. The network interface is configured to transmit the network packet via an associated Ethernet port of the NIC. Other embodiments are described herein.


Find Patent Forward Citations

Loading…