The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Oct. 19, 2020
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Masum Hossain, Edmonton, CA;

Jared L. Zerbe, Woodside, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 25/03 (2006.01); H04L 7/033 (2006.01); H03L 7/00 (2006.01); H03L 7/08 (2006.01); H04L 25/08 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03057 (2013.01); H03L 7/00 (2013.01); H03L 7/0807 (2013.01); H04L 7/0087 (2013.01); H04L 7/033 (2013.01); H04L 25/03038 (2013.01); H04L 25/085 (2013.01);
Abstract

This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.


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