The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Nov. 27, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chung-Pin Huang, New Taipei, TW;

Hou-Yu Chen, Hsinchu County, TW;

Chuan-Li Chen, Yunlin County, TW;

Chih-Kuan Yu, Nantou County, TW;

Yao-Ling Huang, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/823425 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 27/0886 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01); H01L 21/26506 (2013.01);
Abstract

A device comprises a first transistor disposed within a first device region of a substrate and a second transistor disposed within a second device region of the substrate. The first transistor comprises first source/drain regions, a first gate structure laterally between the first source/drain regions, and first gate spacers respectively on opposite sidewalls of the first gate structure. The second transistor comprises second source/drain regions, a second gate structure laterally between the second source/drain regions, and second gate spacers respectively on opposite sidewalls of the second gate structure. The second source/drain regions of the second transistor have a maximal width greater than a maximal width of the first source/drain regions of the first transistor, but the second gate spacers of the second transistor have a thickness less than a thickness of the first gate spacers.


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