The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Jan. 13, 2021
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Shih-Wei Su, Tainan, TW;

Hao-Che Feng, Kaohsiung, TW;

Hsuan-Tai Hsu, Tainan, TW;

Chun-Yu Chen, Taichung, TW;

Wei-Hao Huang, New Taipei, TW;

Bin-Siang Tsai, Changhua County, TW;

Ting-An Chien, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/775 (2006.01); H01L 29/06 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/0243 (2013.01); H01L 21/0245 (2013.01); H01L 21/02507 (2013.01); H01L 21/02532 (2013.01); H01L 21/02639 (2013.01); H01L 21/76224 (2013.01); H01L 21/823481 (2013.01); H01L 29/66439 (2013.01); H01L 29/66742 (2013.01); H01L 21/3065 (2013.01); H01L 29/0673 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method for fabricating a semiconductor device includes the steps of first forming a fin-shaped structure on a substrate, forming a dielectric layer surrounding the fin-shaped structure, performing an anneal process to transform the dielectric layer into a shallow trench isolation (STI), removing the fin-shaped structure to form a trench, and forming a stack structure in the trench. Preferably, the stack structure includes a first semiconductor layer on the fin-shaped structure and a second semiconductor layer on the first semiconductor layer and the first semiconductor layer and the second semiconductor layer include different materials.


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