The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Dec. 14, 2020
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Ashish Jain, Austin, TX (US);

Sriram Sundaram, Austin, TX (US);

Samuel Naffziger, Fort Collins, CO (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 29/50 (2006.01); G11C 7/22 (2006.01); H03K 3/03 (2006.01);
U.S. Cl.
CPC ...
G11C 29/50012 (2013.01); G11C 7/222 (2013.01); H03K 3/0315 (2013.01);
Abstract

The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.


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