The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Dec. 18, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jae-Hak Yun, Suwon-si, KR;

Jae Woo Im, Yongin-si, KR;

Sang-Hyun Joo, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 16/0483 (2013.01); G06F 3/0614 (2013.01); G06F 3/0634 (2013.01); G11C 11/4074 (2013.01);
Abstract

A nonvolatile memory device and an operating method are provided. The nonvolatile memory device includes a memory cell array including a plurality of planes, each plane including a plurality of memory blocks, an address decoder connected to the memory cell array, a voltage generator configured to apply an operating voltage to the address decoder, a page buffer circuit including page buffers corresponding to each of the planes, a data input/output circuit connected to the page buffer circuit configured to input and output data and a control unit configured to control the operation of the address decoder, the voltage generator, the page buffer circuit, and the data input/output circuit, wherein the control unit is configured to operate in a multi-operation or a single operation by checking whether a memory block of an access address is a bad block.


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