The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Jun. 30, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yasushi Matsubara, Isehara, JP;

Yusuke Jono, Musashimurayama, JP;

Donald Martin Morgan, Meridian, ID (US);

Nobuo Yamamoto, Nerima, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/20 (2006.01); G11C 7/18 (2006.01);
U.S. Cl.
CPC ...
G11C 7/065 (2013.01); G11C 7/1027 (2013.01); G11C 7/1039 (2013.01); G11C 7/18 (2013.01); G11C 7/20 (2013.01);
Abstract

Methods, systems, and devices for reading and writing memory management data using a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.


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