The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Aug. 15, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Win-San Khwa, Hsin-Chu, TW;

Yu-Der Chih, Hsin-Chu, TW;

Yi-Chun Shih, Taipei, TW;

Chien-Yin Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/54 (2006.01); G11C 29/04 (2006.01); G06N 3/063 (2006.01); G06N 3/08 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06N 3/08 (2013.01); G11C 11/54 (2013.01); G11C 29/04 (2013.01); G11C 7/1006 (2013.01);
Abstract

Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.


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