The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2022
Filed:
Dec. 21, 2018
Intel Corporation, Santa Clara, CA (US);
Kun Tian, Shanghai, CN;
Sanjay Kumar, Hillsboro, OR (US);
Ashok Raj, Portland, OR (US);
Yi Liu, Beijing, CN;
Rajesh M. Sankaran, Portland, OR (US);
Philip R. Lantz, Cornelius, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Process address space identifier virtualization uses hardware paging hint. The processing device () comprising: a processing core (); and a translation circuit coupled to the processing core, the translation circuit to: receive a workload instruction from a guest application being executed by the processing device, the workload instruction comprising an untranslated guest process address space identifier (gPASID), a workload for an input/output (I/O) target device, and an identifier of a submission register on the I/O target device (), access a paging data structure (PDS) associated with the guest application to retrieve a page table entry corresponding to the gPASID and the identifier of the submission register (), determine a value of an I/O hint bit of the page table entry corresponding to the gPASID and the identifier of the submission register (), responsive to determining that the I/O hint bit is enabled, keep the untranslated gPASID in the workload instruction (), and provide the workload instruction to a work queue of the I/O target device ().