Method, device and terminal for testing memory chip

Abstract

The present disclosure provides a method, a device and a terminal for testing a memory chip. The method may include setting an attack mode and random attack parameters, generating a random attack command according to the attack mode and random attack parameters, attacking the memory chip according to the random attack command, and testing the attacked memory chip and generating a test result. This method is able to simulate various types of attacks and can thus perform a suitable test on the memory chip for the types of the actual attack. In addition, since the attacks can be randomized to any memory cell of the memory chip, testing of the whole memory chip is made possible.