The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2022
Filed:
Jan. 20, 2020
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventor:
J. Thomas Pawlowski, Boise, ID (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 11/10 (2006.01); G06F 13/38 (2006.01); G06F 11/07 (2006.01); G11C 29/52 (2006.01); H04L 1/18 (2006.01); H04L 47/12 (2022.01); H04L 47/25 (2022.01); H04L 47/52 (2022.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/061 (2013.01); G06F 3/0604 (2013.01); G06F 3/0611 (2013.01); G06F 3/0617 (2013.01); G06F 3/0644 (2013.01); G06F 3/0655 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 3/0679 (2013.01); G06F 3/0683 (2013.01); G06F 3/0685 (2013.01); G06F 3/0688 (2013.01); G06F 11/07 (2013.01); G06F 11/073 (2013.01); G06F 11/076 (2013.01); G06F 11/0727 (2013.01); G06F 11/10 (2013.01); G06F 11/1016 (2013.01); G06F 11/1044 (2013.01); G06F 11/1068 (2013.01); G06F 11/1072 (2013.01); G06F 13/16 (2013.01); G06F 13/38 (2013.01); G11C 29/52 (2013.01); H04L 1/189 (2013.01); H04L 47/12 (2013.01); H04L 47/25 (2013.01); H04L 47/52 (2013.01); Y02D 10/00 (2018.01);
Abstract
A memory device includes a memory component that stores data. The memory device also includes a processor that receives a signal indicating that the memory component is coupled to the processor and retrieves information from the memory component. The information may include one or more algorithms capable of being performed by the memory component. The processor may then receive one or more packets associated with one or more data operations regarding the memory component. The processor may then perform the one or more data operations by using the memory component to employ the one or more algorithms.