The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Jan. 19, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Joshua T. Smith, Croton on Hudson, NY (US);

William Francis Landers, Wappingers Falls, NY (US);

Kevin Winstel, East Greenbush, NY (US);

Teresa Jacqueline Wu, Rexford, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81C 1/00 (2006.01); B01L 3/00 (2006.01); B81B 1/00 (2006.01); B01D 15/34 (2006.01); G01N 27/447 (2006.01); G01N 30/60 (2006.01);
U.S. Cl.
CPC ...
B01L 3/502761 (2013.01); B01D 15/34 (2013.01); B01L 3/502707 (2013.01); B01L 3/502715 (2013.01); B01L 3/502753 (2013.01); B81B 1/00 (2013.01); G01N 27/44704 (2013.01); G01N 27/44773 (2013.01); B01L 2200/027 (2013.01); B01L 2200/0689 (2013.01); B01L 2200/12 (2013.01); B01L 2300/0816 (2013.01); B01L 2300/0887 (2013.01); B01L 2300/12 (2013.01); B81C 1/00119 (2013.01); G01N 27/44791 (2013.01); G01N 30/6095 (2013.01);
Abstract

Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.


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