The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

Mar. 30, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Keith Underwood, Powell, TN (US);

Karl Brummel, Chicago, IL (US);

John Greth, Hudson, MA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 49/901 (2022.01); H04L 45/745 (2022.01); H04L 49/35 (2022.01); H04L 67/568 (2022.01); H04L 49/9047 (2022.01); H04L 69/04 (2022.01);
U.S. Cl.
CPC ...
H04L 49/901 (2013.01); H04L 45/745 (2013.01); H04L 49/355 (2013.01); H04L 67/568 (2022.05); H04L 49/9047 (2013.01); H04L 69/04 (2013.01);
Abstract

Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.


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