The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

Aug. 18, 2017
Applicant:

Telefonaktiebolaget Lm Ericsson (Publ), Stockholm, SE;

Inventors:

Neng Liu, Montreal, CA;

Robert Brunner, Montreal, CA;

Stephane Lessard, Mirabel, CA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01Q 1/22 (2006.01); G02B 6/43 (2006.01); H01L 23/48 (2006.01); H01L 23/66 (2006.01); H01L 25/16 (2006.01); G02F 1/015 (2006.01);
U.S. Cl.
CPC ...
H01Q 1/2283 (2013.01); G02B 6/43 (2013.01); H01L 23/481 (2013.01); H01L 23/66 (2013.01); H01L 25/167 (2013.01); G02F 1/015 (2013.01); G02F 1/0157 (2021.01); H01L 2223/6616 (2013.01); H01L 2223/6677 (2013.01);
Abstract

A radio-frequency three-dimensional electronic-photonic integrated circuit (RF 3D EPIC) comprises a radio-frequency (RF) photonic integrated circuit (PIC) layer, the RF PIC layer comprising, in a single integrated circuit, at least one RF antenna and at least one photonic device coupling the RF antenna to an optical interface, and further comprises an electronic-photonic integrated circuit (EPIC) assembly optically coupled to the optical interface of the RF PIC layer, the EPIC assembly comprising two or more integrated-circuit dies bonded to one another so as to form a die stack, wherein at least one of the two or more integrated-circuit dies comprises one or more integrated photonic devices and wherein each of the two or more integrated-circuit dies is electrically connected to at least one other integrated-circuit die via an electrically conductive through-wafer interconnect or an electrically conductive through-wafer via.


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