The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

May. 25, 2021
Applicant:

Industry-university Cooperation Foundation Hanyang University, Seoul, KR;

Inventors:

Yun Heub Song, Seongnam-si, KR;

Sun Jun Choi, Namyangju-si, KR;

Chang Hwan Choi, Seoul, KR;

Jae Kyeong Jeong, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); H01L 27/11597 (2017.01); H01L 29/24 (2006.01); H01L 29/51 (2006.01); H01L 27/1159 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11597 (2013.01); G11C 11/223 (2013.01); G11C 11/2259 (2013.01); G11C 11/2275 (2013.01); H01L 27/1159 (2013.01); H01L 29/24 (2013.01); H01L 29/516 (2013.01);
Abstract

Provided are a three-dimensional semiconductor memory device, a method for manufacturing the same, a method for operating the same, and an electronic system including the same. The three-dimensional semiconductor memory device includes a substrate, a stack structure on the substrate, and vertical channel structures, which are provided in channel holes penetrating the stack structure, wherein each of the vertical channel structures includes a data storage pattern, a vertical channel pattern, a conductive pad, and a vertical semiconductor pattern, wherein the vertical channel pattern includes a first portion contacting the upper surface of the substrate and a second portion provided between the data storage pattern and the vertical semiconductor pattern, and wherein the vertical semiconductor pattern is spaced apart from the substrate with the first portion of the vertical channel pattern therebetween.


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